Semiconductor technology and chip manufacturing advances have resulted in a steady decrease of chip feature size to increase on-chip circuit switching frequency (circuit performance) and the number of transistors (circuit density). Generally, all other factors being constant, the active power consumed by a given unit increases linearly with switching frequency. Thus, not withstanding the decrease of chip supply voltage, chip power consumption has increased as well. Both at the chip and system levels, cooling and packaging costs have escalated as a natural result of this increase in chip power. For low end systems (e.g., handhelds, portable and mobile systems), where battery life is crucial, reducing net power consumption is important but, such a power reduction must come without degrading chip/circuit performance below acceptable levels.
To minimize semiconductor circuit power consumption, most integrated circuits (ICs) are made in the well-known complementary insulated gate Field Effect Transistor (FET) technology known as CMOS. A typical CMOS circuit includes paired complementary devices, i.e., an n-type FET (NFET) paired with a corresponding p-type FET (PFET), usually gated by the same signal. Since the pair of devices have operating characteristics that are, essentially, opposite each other, when one device (e.g., the NFET) is on and conducting (ideally modeled as a resistor (R) in series with the closed switch), the other device (the PFET) is off, not conducting (ideally modeled as an open switch) and, vice versa. Thus, ideally, there is no static or DC current path in a typical CMOS circuit.
A CMOS inverter, for example, is a PFET and NFET pair that are series connected between a power supply voltage (Vdd) and ground (GND). Both are gated by the same input and both drive the same output, typically a capacitive load. The PFET pulls the output high and the NFET pulls the output low at opposite input signal states. Ideally, when the gate of a NFET is below some positive threshold voltage (VT) with respect to its source, the NFET is off, i.e., the switch is open. Above VT, the NFET is on conducting current, i.e., the switch is closed. Similarly, a PFET is off when its gate is above its VT, i.e., less negative, and on below VT. So, ideal CMOS circuits use no static or DC power and primarily consume transient power from charging and discharging capacitive loads.
Random access memories (RAMs) are well known in the art. A typical RAM has a memory array of rows (word lines) and columns (bit lines) of cell locations wherein every location is addressable and freely accessible by providing the correct corresponding address. Dynamic RAMs (DRAMs) are dense RAMs with a very small memory cell. DRAM arrays, increasingly, are being embedded in logic and included on CMOS logic chips, e.g. in on-chip, processor or microprocessor cache memory. Essentially, a DRAM cell is a capacitor for storing charge and a switch, a pass transistor (also called a pass gate or access transistor) that switches on and off to transfer charge to and from the capacitor. Data (1 bit) stored in the cell is determined by the absence or presence of charge on the storage capacitor. Since each cell has numerous leakage paths from the storage capacitor, unless it is periodically refreshed, charge stored on the storage capacitor eventually leaks off.
Each DRAM cell is read by coupling the cell's storage capacitor (through the access transistor) to a bit line, which is a larger capacitance. A signal develops on the bit line that reflects the contents of the cell. Typically, the signal is a bit line voltage difference (determined by ratio of the cell and bit line capacitances) when the cell storage capacitor voltage does not match the bit line; and no difference when the voltages match. A sense amplifier measures the resulting bit line voltage difference, and develops a fully complementary signal from the bit line signal. For a typical segmented data path, the sense amplifier drives that fully complementary signal on a global data line that may also be a complementary pair of lines, each of which is a much larger capacitance than the bit line capacitance, normally, driving one of the pair low/high with the other of the pair remaining high/low. The global data line, in turn, may be an input to a driver, a latch, etc. that passes the data contents external to the DRAM, e.g., to chip logic for an eDRAM. Writing to a cell is, essentially, the reverse, i.e., driving one of the global bit line pair low/high, coupling the driven global line to the bit line and the bit line to the cell. Consequently, charging and discharging data path capacitance in each access (read/write) can consume an appreciable amount of power, to significantly increase chip power consumption.
Thus, there is a need for reducing power in high performance DRAMs, and more particularly, for reducing power in high performance DRAMs suitable for embedded use in logic chips.